//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : 
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths


module AURG_WRSYNC_RAM384_12_12(
   input                      CLKA,
   input                      WEA,
   input[4:0]                 ADDRA,
   input[11:0]                DINA,

   input                      CLKB,
   input[4:0]                 ADDRB,
   output[11:0]               DOUTB
   );


AUPP_XLNX_RAM384_12_12             INST_RAM384_12_12(
   .clk                            ( CLKA ),
   .we                             ( WEA ),
   .a                              ( ADDRA[4:0] ),
   .d                              ( DINA[11:0] ),
   .qdpo_clk                       ( CLKB ),
   .dpra                           ( ADDRB[4:0] ),
   .qdpo                           ( DOUTB[11:0] )
   );

endmodule
